1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to electrically erasable programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) cells.
2. Description of Related Art
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
Semiconductor process technology has continued to move toward defining smaller device features, and the conventional xe2x80x9cstacked gatexe2x80x9d EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, in EEPROM devices used for programmable logic devices, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
Conventionally, programmable logic EEPROMS were typically formed by stacked gate devices operating utilizing Fowler-Nordheim tunneling to program and erase the floating gate or in single polysilicon- based cells such as that set forth in U.S. Pat. No. 4,924,278. An alternative to the aforementioned Fowler-Nordheim tunneling-based cell structures is a nonvolatile memory cell that is programmed and erased using hot electrons or hot holes generated by Zener/avalanche breakdown over different regions of the cell oxide. One example of such a cell is shown in FIG. 1. The cell and its operation are disclosed in co-pending application Ser. No. 09/220,201 which is hereby specifically incorporated herein by reference.
In the device shown in FIG. 1, hot carriers generated by Zener/avalanche breakdown are employed to program and erase the memory cell. The device includes an (array) control gate ACG, floating gate FG, avalanche/Zener program element Qw, a read transistor Qr, and a sense transistor Qc. The control gate ACG is used to accelerate hot electrons or hot holes selectively to or from the floating gate by capacitively coupling a field across the oxide that separates the avalanche element Qw from the floating gate. Floating gate FG is capacitively coupled to array control gate (ACG) voltage via capacitor 11. Avalanche/Zener program element Qw shares floating gate FG with sense transistor Qc, and includes a first active region 12 and second active region 13.
Sense transistor Qc shares its drain 19 with source 17 of read transistor Qr. Gate 14 of read transistor Qr is connected to word line WL. The drain of read transistor Qr is connected to a read signal select (product term) PT, while the source of sense transistor Qc is connected to sense signal (product term ground) PTG.
Silicon substrate 310 has a first conductivity type such as a P-type conductivity. An avalanche/Zener element Qw is electrically separated from the sense transistor Qc by a first insulated region 150, e.g. silicon dioxide, also formed in the semiconductor substrate 310.
Avalanche/Zener element Qw has first impurity region 13 and a second impurity region 12, all formed within a substrate 310 with a channel 30 positioned thereinbetween. Overlying the channel 30 is an oxide layer 40. The oxide layer 40 is typically composed of an insulating material, such as silicon dioxide, and has a thickness of approximately 80 to 150 angstroms. Oxide layer 40 may be deposited or grown (using conventional oxide deposition techniques) in a single process step. Impurity regions 12 and 13 consist of a heavily doped ( greater than 1017-1020cmxe2x88x922) boron implanted P+ regions. Channel 30 may include a shallowly diffused, N-type impurity doped region 30 with a doping concentration of the N-well 1017cmxe2x88x922, or may be provided with a supplemental implant to specifically adjust the concentration of the channel to a desired level to tailor the breakdown voltage of the device. By heavily doping P+ region 12/13, the junction breakdown voltage Vpp is about 6-8V.
Floating gate FG overlies the program element oxide layer 40 and sense oxide layer 90. Floating gate FG is also formed of a conducting material, such as a polycrystalline silicon material.
The elements Qw, Qc and Qr of EEPROM 10 are electrically coupled to certain electrical lines and gates in order to operate and control the functions of the EEPROM cell 10. As shown in FIG. 1, WBLxcex8 is electrically coupled to the program region 12, WBLp coupled to region 13, and WWL to N+ well 380. A product term ground (PTG) is electrically coupled to the sense source 21 of the sense transistor Qc. A word line read (WL) is electrically coupled to the read gate 14 of the read transistor Qr and a Product Term (PT) is electrically coupled to the read drain 15. Table 1 shows the voltages used in programming (injecting electrons into the floating gate) and erasing (injecting holes into the floating gate) in the device shown in FIG. 1:
Note that for a PMOS device, the WBLE,P voltage and WWL voltages for an erase mode may be xe2x88x926V, 0V respectively or 0V and +6V respectively.) A significant advantage of the N-well configuration shown in FIG. 1 is the isolation of cell Qw with respect to other cells in an array. A further advantage is that hot electron/hole injection element can be scaled to smaller dimensions than traditional Fowler-Nordheim cells. Even with the scaling advantages presented by the EEPROM-type cells, designers constantly seek to improve the performance of such cells.
The invention, roughly described, comprises a non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a second active region of a second conductivity type, separated by a channel region of said second conductivity type; a second avalanche injection element having a third active region of said second conductivity type and sharing said second active region with said first avalanche injection element, the second avalanche injection element having a channel region of said first conductivity type; and a common floating gate at least partially overlying said first and second avalanche injection elements.
In a further embodiment, the invention describes a memory cell comprising a first avalanche element having an N+/P junction, a second avalanche element having a P+/N junction, and a floating gate capacitively coupled to the first and second avalanche elements.
In yet another embodiment of the invention, in an array of non-volatile memory cells, each cell comprises a first program junction having a high concentration of a first conductivity type adjoining a region of a second conductivity type; a second program junction having a high concentration of said second conductivity type adjoining a region of said first conductivity type; and a floating gate overlying at least a portion of said first and second junctions.